A basic building block of a radio frequency (RF) communication receiver is the mixer. A mixer down-converts an RF signal received at an antenna to an intermediate frequency (IF)—or in some receiver designs, directly down-converts the received RF signal into a zero intermediate frequency (ZIF)—by multiplying the received signal with a local oscillator (LO) signal. A receiver using ZIF is also called homodyne or “direct conversion” receiver. A direct conversion receiver is easier to integrate on a chip than IF designs, as it eliminates pass-band filters and reduces the space and complexity as well as cost.
A typical prior art receiver architecture 140 is depicted in FIG. 11. A received RF signal is amplified by a low noise amplifier (LNA) 142. A Balun 144 transforms the received signal to one balanced about ground. In-phase (I) and quadrature (Q) mixers 146 down-convert the balanced RF signals to baseband by mixing the I and Q components, respectively, with clock signals having a 90-degree phase offset, from a local oscillator or clock generator/driver 148. The baseband signals are then filtered by baseband low pass filters 150 to remove high frequency harmonics.
Mixers 146 in practice may be designed as either active or passive circuits. Active mixers can provide gain while down-converting the RF signal, but are generally less linear and have higher noise figures. In particular, the flicker noise contribution is higher, which is harmful for narrow-band RF applications like GSM.
RF communication systems usually demand a duplex operation mode in a transceiver, in which the receiver 140 and a transmitter work simultaneously. As the transmitter sends signals at high power levels, the receiver 140 will suffer from interference. As a result, very good linearity is required for both the LNA 142 and the mixer(s) 146. This is particularly true for the mixer 146, as the RF signal is amplified by the LNA 142. For a direct conversion receiver 140, protecting the receiver 140 from the interference created by a transmitter is very important. In particular, the second order inter-modulation product, IM2, must be kept low. The measure of this is known as the second order input intercept point (IIP2).
In order to obtain better IIP2, it is known to process differential RF signals in a balanced, or symmetric topology, to cancel out nonlinearities caused by the devices (e.g., transistors). Thus, a balun 144 is employed to perform single-end to differential conversion of the input RF signal. Ideally, the even orders of nonlinear distortions of differential signals could be cancelled between balanced positive and negative output nodes. This requires a perfect match between the transistors used in mixer cores 146 as well as the clock drivers 148. In practice, any mismatch of transistors in mixer cores 146 and/or the clock drivers 148 will lead to limited suppression of IM2.
One known approach to reducing the over-all component mismatch is to decrease the device spread by scaling up the device sizes. However, this approach has the disadvantage of consuming larger chip area, and more seriously also results in larger power consumption due to increased capacitive loading.
For quadrature mixer operation, as shown in FIG. 11, a two-phase clock scheme does not work well, since the two output loads will interact with each other, resulting in lower conversion gain, lower linearity, and IQ leakage. Therefore, good isolation between the I and Q channels is required. One known remedy is to use a four-phase clock scheme, wherein four conducting time slots are non-overlapped and evenly spaced between I and Q without short-circuiting the two loads.